Hi Kevin,
On Thu, 2 Mar 2023 09:37:30 +0000, "Tian, Kevin" <kevin.tian@xxxxxxxxx>
wrote:
> > From: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
> > Sent: Thursday, March 2, 2023 9:00 AM
> >
> > @@ -4675,6 +4679,33 @@ static void
> > intel_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid)
> > intel_pasid_tear_down_entry(iommu, dev, pasid, false);
> > }
> >
> > +static int intel_iommu_set_dev_pasid(struct iommu_domain *domain,
> > + struct device *dev, ioasid_t pasid)
> > +{
> > + struct device_domain_info *info = dev_iommu_priv_get(dev);
> > + struct dmar_domain *dmar_domain = to_dmar_domain(domain);
> > + struct intel_iommu *iommu = info->iommu;
> > + int ret = 0;
> > +
> > + if (!sm_supported(iommu) || !info)
> > + return -ENODEV;
> > +
> > + if (WARN_ON(pasid == PASID_RID2PASID))
> > + return -EINVAL;
> > +
> > + if (hw_pass_through && domain_type_is_si(dmar_domain))
> > + ret = intel_pasid_setup_pass_through(iommu,
> > dmar_domain,
> > + dev, pasid);
> > + else if (dmar_domain->use_first_level)
> > + ret = domain_setup_first_level(iommu, dmar_domain,
> > + dev, pasid);
> > + else
> > + ret = intel_pasid_setup_second_level(iommu,
> > dmar_domain,
> > + dev, pasid);
> > +
>
> check whether pasid capability has been enabled on this device.
>
> it's unlike SVA which has separate capability to tell.
yes, it is a little tricky in that enabling PASID should be done before ATS
but for now anything uses ENQCMDS should support ATS. I will add
/*
* PASID should be enabled as part of PCI caps enabling where
* ordering is required relative to ATS.
*/
if (WARN_ON(!pdev->pasid_enabled))
return -ENODEV;
Thanks,
Jacob
