On 13 2月 23 14:59:27, Bjorn Helgaas wrote:
> On Mon, Feb 13, 2023 at 09:24:08PM +0800, Cai Huoqing wrote:
> > From: Cai huoqing <cai.huoqing@xxxxxxxxx>
> >
> > Add support for HDMA NATIVE, as long the IP design has set
> > the compatible register map parameter-HDMA_NATIVE,
> > which allows compatibility for native HDMA register configuration.
>
> Rewrap to fill 75 columns. Also applies below.
>
> > The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
> > And the native HDMA registers are different from eDMA,
> > so this patch add support for HDMA NATIVE mode.
> >
> > HDMA write and read channels operate independently to maximize
> > the performance of the HDMA read and write data transfer over
> > the link When you configure the HDMA with multiple read channels,
> > then it uses a round robin (RR) arbitration scheme to select
> > the next read channel to be serviced.
> > The same applies when you have multiple write channels.
>
> Wrap into a single paragraph or add a blank line if you want the last
> sentence to be a new paragraph.
>
> > The native HDMA driver also supports a maximum of 16 independent
> > channels (8 write + 8 read), which can run simultaneously.
> > Both SAR (Source Address Register) and DAR (Destination Address Register)
> > are alignmented to byte.
>
> s/alignmented/aligned/
>
> > + u32 watermark_en; /* 0x0030 */
> > + u32 control1; /* 0x0034 */
> > + u32 func_num; /* 0x0038 */
> > + u32 qos; /* 0x003c */
> > + u32 reserved; /* 0x0040..0x007c */
> > + u32 ch_stat; /* 0x0080 */
>
> Weird indentation of control1, func_num, etc. Is that meaningful or a
> mistake?
>
> > + union {
> > + u64 reg; /* 0x00a0..0x00a4 */
> > + struct {
> > + u32 lsb; /* 0x00a0 */
> > + u32 msb; /* 0x00a4 */
> > + };
> > + } msi_abort;
> > + u32 msi_msgdata; /* 0x00a8 */
>
> Again here.
Will fix these in next version
Cai
>
> Bjorn
