On Sun, Oct 09, 2022 at 09:13:36PM +0300, Siarhei Volkau wrote: > These SoCs are close to others but they have a clock divisor /2 for low > clock peripherals, thus to set up a proper baud rate we need to take > this into account. > > The divisor bit is located in CGU area, unfortunately the clk framework > can't be used at early boot steps, so it's checked by direct readl() > call. > > Signed-off-by: Siarhei Volkau <lis8215@xxxxxxxxx> > --- > drivers/tty/serial/8250/8250_ingenic.c | 39 ++++++++++++++++++++++---- > 1 file changed, 34 insertions(+), 5 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c > index 2b2f5d8d2..f2662720d 100644 > --- a/drivers/tty/serial/8250/8250_ingenic.c > +++ b/drivers/tty/serial/8250/8250_ingenic.c > @@ -70,7 +70,8 @@ static void ingenic_early_console_write(struct console *console, > ingenic_early_console_putc); > } > > -static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev) > +static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev, > + int clkdiv) What does "clkdiv" mean here? And this function is rough, adding a random integer to a function requires you to look it up every time you see this call. If you only have 1 or 2 as an option, just have 2 functions instead please. thanks, greg k-h
