On Mon, Aug 22, 2022 at 09:53:32PM +0300, Serge Semin wrote:
> Since the DW eDMA driver now supports eDMA controllers embedded into the
> locally accessible DW PCIe Root Ports and Endpoints, we can use the
> updated interface to register DW eDMA as DMA engine device if it's
> available. In order to successfully do that the DW PCIe core driver need
> to perform some preparations first. First of all it needs to find out the
> eDMA controller CSRs base address, whether they are accessible over the
> Port Logic or iATU unrolled space. Afterwards it can try to auto-detect
> the eDMA controller availability and number of it's read/write channels.
s/it's//
> If none was found the procedure will just silently halt with no error
> returned. Secondly the platform is supposed to provide either combined or
> per-channel IRQ signals. If no valid IRQs set is found the procedure will
> also halt with no error returned so to be backward compatible with the
> platforms where DW PCIe controllers have eDMA embedded but lack of the
> IRQs defined for them. Finally before actually probing the eDMA device we
> need to allocate LLP items buffers. After that the DW eDMA can be
> registered. If registration is successful the info-message regarding the
> number of detected Read/Write eDMA channels will be printed to the system
> log in the similar way as it's done for the iATU settings.
s/in the similar way as it's done/as is done/
> +static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> +{
> + u32 val;
> +
> + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> + if (val == 0xFFFFFFFF && pci->edma.reg_base) {
> + pci->edma.mf = EDMA_MF_EDMA_UNROLL;
> +
> + val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
> + } else if (val != 0xFFFFFFFF) {
Consider PCI_POSSIBLE_ERROR() as an annotation about the meaning of
0xFFFFFFFF and something to grep for.
> + pci->edma.mf = EDMA_MF_EDMA_LEGACY;
> +
> + pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
> + } else {
> + return -ENODEV;
> + }
> + * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
> + * over the Port Logic registers space. Afterwords the unrolled mapping was
s/Afterwords/Afterwards/
> + * introduced so eDMA and iATU could be accessed via a dedicated registers
> + * space.
