Hi Biju,
On Thu, Jul 21, 2022 at 6:06 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > Subject: Re: [PATCH v3] dmaengine: sh: rz-dmac: Add device_synchronize
> > callback
> >
> > On Thu, Jul 21, 2022 at 4:49 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > wrote:
> > > Some on-chip peripheral modules(for eg:- rspi) on RZ/G2L SoC use the
> > > same signal for both interrupt and DMA transfer requests.
> > > The signal works as a DMA transfer request signal by setting DMARS,
> > > and subsequent interrupt requests to the interrupt controller are
> > > masked.
> > >
> > > We can re-enable the interrupt by clearing the DMARS.
> > >
> > > This patch adds device_synchronize callback for clearing DMARS and
> > > thereby allowing DMA consumers to switch to interrupt mode.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > ---
> > > v2->v3:
> > > * Fixed commit description
> > > * Added check if the DMA operation has been completed or terminated,
> > > and wait (sleep) if needed.
> >
> > Thanks for the uodate!
> >
> > > --- a/drivers/dma/sh/rz-dmac.c
> > > +++ b/drivers/dma/sh/rz-dmac.c
> > > @@ -12,6 +12,7 @@
> > > #include <linux/dma-mapping.h>
> > > #include <linux/dmaengine.h>
> > > #include <linux/interrupt.h>
> > > +#include <linux/iopoll.h>
> > > #include <linux/list.h>
> > > #include <linux/module.h>
> > > #include <linux/of.h>
> > > @@ -630,6 +631,21 @@ static void rz_dmac_virt_desc_free(struct
> > virt_dma_desc *vd)
> > > */
> > > }
> > >
> > > +static void rz_dmac_device_synchronize(struct dma_chan *chan) {
> > > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
> > > + struct rz_dmac *dmac = to_rz_dmac(chan->device);
> > > + u32 chstat;
> > > + int ret;
> > > +
> > > + ret = read_poll_timeout(rz_dmac_ch_readl, chstat, !(chstat &
> > CHSTAT_EN),
> > > + 10, 1000, false, channel, CHSTAT, 1);
> >
> > Isn't 1000 µs = 1 ms a bit short?
> > IIUIC, I can submit a DMA operation for transfering a 64 KiB (or larger)
> > block, and call dmaengine_synchronize() immediately after that?
>
> Will increase to 100 msec?? is it ok?
Probably. As this is a sleeping wait, it doesn't hurt to be conservative.
Do you know what's the maximum transfer size/maximum time a DMA
transfer could take?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
