On Fri, Apr 22, 2022 at 09:36:38AM -0500, Frank Li wrote:
> There are same name wr(rd)_ch_cnt in struct dw_edma. EDMA driver get
> write(read) channel number from register, then save these into dw_edma.
> Old wr(rd)_ch_cnt in dw_edma_chip actuall means how many link list memory
> are available in ll_region_wr(rd)[EDMA_MAX_WR_CH]. So rename it to
> ll_wr(rd)_cnt to indicate actual usage.
>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
One minor comment below,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> ---
> Change from v6 to v9
> - none
> Change from v5 to v6
> - s/rename/Rename/ at subject
> new patch at v4
>
> drivers/dma/dw-edma/dw-edma-core.c | 4 ++--
> drivers/dma/dw-edma/dw-edma-pcie.c | 12 ++++++------
> include/linux/dma/edma.h | 8 ++++----
> 3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
> index 435e4f2ab6575..1a0a98f6c5515 100644
> --- a/drivers/dma/dw-edma/dw-edma-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-core.c
> @@ -919,11 +919,11 @@ int dw_edma_probe(struct dw_edma_chip *chip)
>
> raw_spin_lock_init(&dw->lock);
>
> - dw->wr_ch_cnt = min_t(u16, chip->wr_ch_cnt,
> + dw->wr_ch_cnt = min_t(u16, chip->ll_wr_cnt,
> dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE));
> dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH);
>
> - dw->rd_ch_cnt = min_t(u16, chip->rd_ch_cnt,
> + dw->rd_ch_cnt = min_t(u16, chip->ll_rd_cnt,
> dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ));
> dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH);
>
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index ae42bad24dd5a..7732537f96086 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -230,14 +230,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> chip->nr_irqs = nr_irqs;
> chip->ops = &dw_edma_pcie_core_ops;
>
> - chip->wr_ch_cnt = vsec_data.wr_ch_cnt;
> - chip->rd_ch_cnt = vsec_data.rd_ch_cnt;
> + chip->ll_wr_cnt = vsec_data.wr_ch_cnt;
> + chip->ll_rd_cnt = vsec_data.rd_ch_cnt;
>
> chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar];
> if (!chip->reg_base)
> return -ENOMEM;
>
> - for (i = 0; i < chip->wr_ch_cnt; i++) {
> + for (i = 0; i < chip->ll_wr_cnt; i++) {
> struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
> struct dw_edma_region *dt_region = &chip->dt_region_wr[i];
> struct dw_edma_block *ll_block = &vsec_data.ll_wr[i];
> @@ -262,7 +262,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> dt_region->sz = dt_block->sz;
> }
>
> - for (i = 0; i < chip->rd_ch_cnt; i++) {
> + for (i = 0; i < chip->ll_rd_cnt; i++) {
> struct dw_edma_region *ll_region = &chip->ll_region_rd[i];
> struct dw_edma_region *dt_region = &chip->dt_region_rd[i];
> struct dw_edma_block *ll_block = &vsec_data.ll_rd[i];
> @@ -302,7 +302,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> chip->reg_base);
>
>
> - for (i = 0; i < chip->wr_ch_cnt; i++) {
> + for (i = 0; i < chip->ll_wr_cnt; i++) {
> pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
> i, vsec_data.ll_wr[i].bar,
> vsec_data.ll_wr[i].off, chip->ll_region_wr[i].sz,
> @@ -314,7 +314,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> chip->dt_region_wr[i].vaddr, &chip->dt_region_wr[i].paddr);
> }
>
> - for (i = 0; i < chip->rd_ch_cnt; i++) {
> + for (i = 0; i < chip->ll_rd_cnt; i++) {
> pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
> i, vsec_data.ll_rd[i].bar,
> vsec_data.ll_rd[i].off, chip->ll_region_rd[i].sz,
> diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
> index e9ce652b88233..c2039246fc08c 100644
> --- a/include/linux/dma/edma.h
> +++ b/include/linux/dma/edma.h
> @@ -40,8 +40,8 @@ enum dw_edma_map_format {
> * @nr_irqs: total dma irq number
> * @ops DMA channel to IRQ number mapping
> * @reg_base DMA register base address
> - * @wr_ch_cnt DMA write channel number
> - * @rd_ch_cnt DMA read channel number
> + * @ll_wr_cnt DMA write link list number
> + * @ll_rd_cnt DMA read link list number
DMA linked list write/read memory regions?
Thanks,
Mani
> * @rg_region DMA register region
> * @ll_region_wr DMA descriptor link list memory for write channel
> * @ll_region_rd DMA descriptor link list memory for read channel
> @@ -56,8 +56,8 @@ struct dw_edma_chip {
>
> void __iomem *reg_base;
>
> - u16 wr_ch_cnt;
> - u16 rd_ch_cnt;
> + u16 ll_wr_cnt;
> + u16 ll_rd_cnt;
> /* link list address */
> struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
> struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
> --
> 2.35.1
>
