[PATCH v3] dmaengine: xilinx_dma: Free descriptor lists in order

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Subject: [PATCH v3] dmaengine: xilinx_dma: Free descriptor lists in order
From: Nicholas Graumann <nick.graumann@xxxxxxxxx>
Date: Mon, 11 Apr 2022 09:03:48 -0500

If xilinx_dma_terminate_all is called while the AXI DMA is active, the
following error messages might be seen upon restarting the DMA:

[   72.556254] xilinx_dma_irq_handler: Channel d053cb5b has errors 10, cdr 2c049f80 tdr 2c04a000
[   72.557370] xilinx_dma_irq_handler: Channel d053cb5b has errors 100, cdr 2c049f80 tdr 2c049f80

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