Hi Sascha,
-----Original Message-----
From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Sent: 2022年4月5日 16:00
To: alsa-devel@xxxxxxxxxxxxxxxx
Cc: Xiubo Li <Xiubo.Lee@xxxxxxxxx>; Fabio Estevam <festevam@xxxxxxxxx>; Shengjiu Wang <shengjiu.wang@xxxxxxxxx>; kernel@xxxxxxxxxxxxxx; Vinod Koul <vkoul@xxxxxxxxxx>; dl-linux-imx <linux-imx@xxxxxxx>; dmaengine@xxxxxxxxxxxxxxx; Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Subject: [EXT] [PATCH v3 11/20] dmaengine: imx-sdma: Add multi fifo support
Caution: EXT Email
The i.MX SDMA engine can read from / write to multiple successive hardware FIFO registers, referred to as "Multi FIFO support". This is needed for the micfil driver and certain configurations of the SAI driver. This patch adds support for this feature.
The number of FIFOs to read from / write to must be communicated from the client driver to the SDMA engine. For this the struct dma_slave_config::peripheral_config field is used.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
Notes:
Changes since v2:
- Use prefix dmaengine:
- document struct sdma_peripheral_config
- add forgotten commit message
Changes since v1:
- Drop unused variable sw_done_sel
- Evaluate sdmac->direction directly instead of storing value in n_fifos
drivers/dma/imx-sdma.c | 57 +++++++++++++++++++++++++++++++++++++
include/linux/dma/imx-dma.h | 20 +++++++++++++
2 files changed, 77 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 0e70843567cef..95367a8a81a51 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -14,6 +14,7 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/types.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
@@ -73,6 +74,7 @@
#define SDMA_CHNENBL0_IMX35 0x200
#define SDMA_CHNENBL0_IMX31 0x080
#define SDMA_CHNPRI_0 0x100
+#define SDMA_DONE0_CONFIG 0x1000
/*
* Buffer descriptor status values.
@@ -180,6 +182,12 @@
BIT(DMA_MEM_TO_DEV) | \
BIT(DMA_DEV_TO_DEV))
+#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
+#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
+
+#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
+#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
+
/**
* struct sdma_script_start_addrs - SDMA script start pointers
*
@@ -441,6 +449,9 @@ struct sdma_channel {
struct work_struct terminate_worker;
struct list_head terminated;
bool is_ram_script;
+ unsigned int n_fifos_src;
+ unsigned int n_fifos_dst;
+ bool sw_done;
};
The struct sdma_peripheral_config can instead the three variable.
#define IMX_DMA_SG_LOOP BIT(0)
@@ -778,6 +789,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
val = readl_relaxed(sdma->regs + chnenbl);
__set_bit(channel, &val);
writel_relaxed(val, sdma->regs + chnenbl);
+
+ /* Set SDMA_DONEx_CONFIG is sw_done enabled */
+ if (sdmac->sw_done) {
+ val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
+ val |= SDMA_DONE0_CONFIG_DONE_SEL;
+ val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
+ writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
+ }
}
static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -1038,6 +1057,10 @@ static int sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_IPU_MEMORY:
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break;
+ case IMX_DMATYPE_MULTI_SAI:
+ per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
+ break;
default:
dev_err(sdma->dev, "Unsupported transfer type %d\n",
peripheral_type); @@ -1214,6 +1237,22 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; }
+static void sdma_set_watermarklevel_for_sais(struct sdma_channel
+*sdmac) {
+ unsigned int n_fifos;
+
+ if (sdmac->sw_done)
+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
+
+ if (sdmac->direction == DMA_DEV_TO_MEM)
+ n_fifos = sdmac->n_fifos_src;
+ else
+ n_fifos = sdmac->n_fifos_dst;
+
+ sdmac->watermark_level |=
+ FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS,
+n_fifos); }
+
static int sdma_config_channel(struct dma_chan *chan) {
struct sdma_channel *sdmac = to_sdma_chan(chan); @@ -1250,6 +1289,10 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
} else {
+ if (sdmac->peripheral_type ==
+ IMX_DMATYPE_MULTI_SAI)
+ sdma_set_watermarklevel_for_sais(sdmac);
+
__set_bit(sdmac->event_id0, sdmac->event_mask);
}
@@ -1707,9 +1750,23 @@ static int sdma_config(struct dma_chan *chan,
struct dma_slave_config *dmaengine_cfg) {
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
+ if (dmaengine_cfg->peripheral_config) {
+ struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
+ if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
+ dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
+ dmaengine_cfg->peripheral_size,
+ sizeof(struct sdma_peripheral_config));
+ return -EINVAL;
+ }
+ sdmac->n_fifos_src = sdmacfg->n_fifos_src;
+ sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
+ sdmac->sw_done = sdmacfg->sw_done;
+ }
+
/* Set ENBLn earlier to make sure dma request triggered after that */
if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
return -EINVAL;
diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h index b06cba85a6d46..8887762360d40 100644
--- a/include/linux/dma/imx-dma.h
+++ b/include/linux/dma/imx-dma.h
@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
IMX_DMATYPE_SAI, /* SAI */
+ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
};
enum imx_dma_prio {
@@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
!strcmp(chan->device->dev->driver->name, "imx-dma"); }
+/**
+ * struct sdma_peripheral_config - SDMA config for audio
+ * @n_fifos_src: Number of FIFOs for recording
+ * @n_fifos_dst: Number of FIFOs for playback
+ * @sw_done: Use software done. Needed for PDM (micfil)
+ *
+ * Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
+ * registers. For multichannel recording/playback the SAI/micfil have
+ * one FIFO register per channel and the SDMA engine has to read/write
+ * the next channel from/to the next register and wrap around to the
+ * first register when all channels are handled. The number of active
+ * channels must be communicated to the SDMA engine using this struct.
+ */
+struct sdma_peripheral_config {
+ int n_fifos_src;
+ int n_fifos_dst;
+ bool sw_done;
+};
+
The fifos may not be continuous.
Follow the Wang shengjiu suggestion:
"This is our internal definition for this sdma_peripheral_config.
Could you please adopt this?"
/**
* struct sdma_audio_config - special sdma config for audio case
* @src_fifo_num: source fifo number for mcu_2_sai/sai_2_mcu script
* For example, if there are 4 fifos, sdma will fetch
* fifos one by one and roll back to the first fifo after
* the 4th fifo fetch.
* @dst_fifo_num: similar as src_fifo_num, but dest fifo instead.
* @src_fifo_off: source fifo offset, 0 means all fifos are continuous, 1
* means 1 word offset between fifos. All offset between
* fifos should be same.
* @dst_fifo_off: dst fifo offset, similar as @src_fifo_off.
* @words_per_fifo: numbers of words per fifo fetch/fill, 0 means
* one channel per fifo, 1 means 2 channels per fifo..
* If 'src_fifo_num = 4' and 'chans_per_fifo = 1', it
* means the first two words(channels) fetch from fifo1
* and then jump to fifo2 for next two words, and so on
* after the last fifo4 fetched, roll back to fifo1.
* @sw_done_sel: software done selector, PDM need enable software done feature
* in mcu_2_sai/sai_2_mcu script.
* Bit31: sw_done eanbled or not
* Bit16~Bit0: selector
* For example: 0x80000000 means sw_done enabled for done0
* sector which is for PDM on i.mx8mm.
*/
struct sdma_audio_config {
u8 src_fifo_num;
u8 dst_fifo_num;
u8 src_fifo_off;
u8 dst_fifo_off;
u8 words_per_fifo;
u32 sw_done_sel;
};
#endif /* __LINUX_DMA_IMX_H */
--
2.30.2
BR
Joy Zou
