Hi Miquel,
On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal
<miquel.raynal@xxxxxxxxxxx> wrote:
> Describe the two DMA controllers available on this SoC.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 {
> status = "disabled";
> };
>
> + dma0: dma-controller@40104000 {
> + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
> + reg = <0x40104000 0x1000>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "hclk";
> + clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
power-domains?
> + dma-channels = <8>;
> + dma-requests = <16>;
> + dma-masters = <1>;
> + #dma-cells = <3>;
<4>? The dmamux bindings say:
+ The first four cells are dedicated to the master DMA
controller. The fifth
+ cell gives the DMA mux bit index that must be set starting from 0. The
+ sixth cell gives the binary value that must be written there, ie. 0 or 1.
> + block_size = <0xfff>;
> + data_width = <3>;
> + status = "disabled";
> + };
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
