On Fri, Feb 18, 2022 at 07:12:23PM +0100, Miquel Raynal wrote: > From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> > > Pausing a partial transfer only causes data to be written to mem that is > a multiple of the memory width setting. > > However, when a DMA client driver finishes DMA early, e.g. due to UART > char timeout interrupt, all data read from the DEV must be written to MEM. > > Therefore, allow the slave to limit the memory width to ensure all data > read from the DEV is written to MEM when DMA is paused. Is this a fix? What happens to the data if you don't do this? As far as I understood the Synopsys DesignWare specification the DMA controller is capable of flushing FIFO in that case on byte-by-byte basis. Do you have an HW integration bug? TL;DR: tell us more about this. ... > + if (sconfig->dst_addr_width && sconfig->dst_addr_width < data_width) > + data_width = sconfig->dst_addr_width; But here no check that you do it for explicitly peripheral to memory, so this will affect memory to peripheral transfers as well. -- With Best Regards, Andy Shevchenko
