On Tue, Jan 18, 2022 at 10:04:48AM +0800, Hillf Danton wrote: > > > > 5) What DMA Engine enabled drivers (and dmatest) should use as design > > > > pattern to conform migration/cache behavior? Does scheduler optimisation > > > > conflict to DMA Engine performance in general? > > > > > > > > > > I'm not familiar with DMA engine drivers but if they use wake_up > > > interfaces then passing WF_SYNC or calling the wake_up_*_sync helpers > > > may force the migration. > > > > > > > Thanks for the advice. I'll try to check if this is a solution. > > Check if cold cache provides some room for selecting CPU. > > Only for thoughts now. > That will still favour migrating tasks between CPUs that share LLC cache at the expense of losing some higher level caches and cpufreq state (depending on the CPUfreq governor). -- Mel Gorman SUSE Labs
