On Mon, Oct 25, 2021 at 10:10:43PM +0530, Akhil R wrote: > Add DT binding document for Nvidia Tegra GPCDMA controller. > > Signed-off-by: Rajesh Gumasta <rgumasta@xxxxxxxxxx> > Signed-off-by: Akhil R <akhilrajeev@xxxxxxxxxx> > Reviewed-by: Jon Hunter <jonathanh@xxxxxxxxxx> > --- > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 108 +++++++++++++++++++++ > 1 file changed, 108 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > new file mode 100644 > index 0000000..d3f58d8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings > + > +description: | > + The Tegra General Purpose Central (GPC) DMA controller is used for faster > + data transfers between memory to memory, memory to device and device to > + memory. > + > +maintainers: > + - Jon Hunter <jonathanh@xxxxxxxxxx> > + - Rajesh Gumasta <rgumasta@xxxxxxxxxx> > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + compatible: > + oneOf: > + - enum: > + - nvidia,tegra186-gpcdma > + - nvidia,tegra194-gpcdma > + - items: > + - const: nvidia,tegra186-gpcdma > + - const: nvidia,tegra194-gpcdma > + > + "#dma-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 32 One per channel or what? You must define what each one is. > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: gpcdma > + > + iommus: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - resets > + - reset-names > + - "#dma-cells" > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/tegra186-mc.h> > + #include <dt-bindings/reset/tegra186-reset.h> > + > + gpcdma:dma-controller@2600000 { Drop unused labels. > + compatible = "nvidia,tegra186-gpcdma"; > + reg = <0x2600000 0x0>; > + resets = <&bpmp TEGRA186_RESET_GPCDMA>; > + reset-names = "gpcdma"; > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; > + dma-coherent; > + }; > +... > -- > 2.7.4 > >
