On 07-01-21, 19:15, Geert Uytterhoeven wrote:
> The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from
> the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs:
> 1. The per-channel registers are located in a second register block.
> Add support for mapping the second block, using the appropriate
> offsets and stride.
> 2. The common Channel Clear Register (DMACHCLR) was replaced by a
> per-channel register.
> Update rcar_dmac_chan_clear{,_all}() to handle this.
> As rcar_dmac_init() needs to clear the status before the individual
> channels are probed, channel index and base address initialization
> are moved forward.
>
> Inspired by a patch in the BSP by Phong Hoang
> <phong.hoang.wz@xxxxxxxxxxx>.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> drivers/dma/sh/rcar-dmac.c | 68 +++++++++++++++++++++++++++-----------
> 1 file changed, 49 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
> index 990d78849a7de704..c11e6255eba1fc6b 100644
> --- a/drivers/dma/sh/rcar-dmac.c
> +++ b/drivers/dma/sh/rcar-dmac.c
> @@ -189,7 +189,7 @@ struct rcar_dmac_chan {
> * struct rcar_dmac - R-Car Gen2 DMA Controller
> * @engine: base DMA engine object
> * @dev: the hardware device
> - * @iomem: remapped I/O memory base
> + * @iomem: remapped I/O memory bases (second is optional)
> * @n_channels: number of available channels
> * @channels: array of DMAC channels
> * @channels_mask: bitfield of which DMA channels are managed by this driver
> @@ -198,7 +198,7 @@ struct rcar_dmac_chan {
> struct rcar_dmac {
> struct dma_device engine;
> struct device *dev;
> - void __iomem *iomem;
> + void __iomem *iomem[2];
do you forsee many more memory regions, if not then why not add second
region, that way changes in this patch will be lesser..?
and it would be better to refer to a region by its name rather than
iomem[1]..
--
~Vinod
