On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote: > On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote: > > > Not randomly put there Jason :-).. There is a good reason for it. > > Sure the PASID value being associated with the IRQ make sense, but > combining that register with the interrupt mask is just a compltely > random thing to do. Hummm... Not sure what you are complaining.. but in any case giving hardware a more efficient way to store interrupt entries breaking any boundaries that maybe implied by the spec is why IMS was defined. > > If this HW was using MSI-X PASID would have been given its own > register. Well there is no MSI-X PASID is there?
