On Thu, Sep 24, 2020 at 10:42:16AM +0000, David Laight wrote:
> The movdir64b instruction does a 'normal' read of 64 bytes (can be
> misaligned) Then a cache-bypassing (probably) write-combining single
> 64byte write to an address that must be aligned. Any reference to
> segment registers is largely irrelevant since we are not in real mode.
Sounds like you know better than the SDM.
> Mainly less lines of code to look at.
Yeah, no. Readability is what I would prefer any day of the week.
> No idea what clwb() is doing.
Sounds like you need to read another part of the SDM.
> But the "+m" (dst) tells gcc it depends on, and modifies the 64 bytes
> at *dst.
>
> I believe the 'volatile' is pointless.
I discussed this at the time with a gcc person. And nope, it ain't
pointless.
> No, that just says the asm uses the value of the pointer.
> Not what it points to.
Err, no, it is *exactly* what it points to that is important here and
you're telling the compiler that the instruction will read that much
memory through the pointer.
Ok, I've read enough babble. I'll discuss it with a gcc person before I
take anything.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
