I've attached a patch below. When using this patch with the xilinx-v2019.2.01 tag I get a kernel panic immediately when loading the module. Maybe the exact components on the FPGA are also important. I have one AXI DMA component with scatter/gather enabled, read/write widths set to 64bit and a max burst size of 16. diff --git a/drivers/dma/xilinx/axidmatest.c b/drivers/dma/xilinx/axidmatest.c index 3d88982c9f7e..757bab152e0a 100644 --- a/drivers/dma/xilinx/axidmatest.c +++ b/drivers/dma/xilinx/axidmatest.c @@ -407,6 +407,7 @@ static int dmatest_slave_func(void *data) dma_async_issue_pending(tx_chan); dma_async_issue_pending(rx_chan); + dma_sync_wait(tx_chan, tx_cookie); tx_tmo = wait_for_completion_timeout(&tx_cmp, tx_tmo); status = dma_async_is_tx_complete(tx_chan, tx_cookie, @@ -428,6 +429,7 @@ static int dmatest_slave_func(void *data) continue; } + dma_sync_wait(rx_chan, rx_cookie); rx_tmo = wait_for_completion_timeout(&rx_cmp, rx_tmo); status = dma_async_is_tx_complete(rx_chan, rx_cookie, NULL, NULL);
