On 09/02/2020 16:33, Dmitry Osipenko wrote:
> Technically it is possible that DMA could be misconfigured in a way that
> cyclic DMA transfer is processed slower than it takes to complete the
> cycle and in this case the DMA is getting aborted with a not very
> informative message about the problem, let's improve it.
>
> Suggested-by: Jon Hunter <jonathanh@xxxxxxxxxx>
> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> ---
> drivers/dma/tegra20-apb-dma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index 3e0373b89195..1a9b37c102ba 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -566,7 +566,7 @@ static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
> if (!hsgreq->configured) {
> tegra_dma_stop(tdc);
> pm_runtime_put(tdc->tdma->dev);
> - dev_err(tdc2dev(tdc), "Error in DMA transfer, aborting DMA\n");
> + dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n");
> tegra_dma_abort_all(tdc);
> return false;
> }
>
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Thanks!
Jon
--
nvpublic
