On 25-11-19, 12:12, Radhey Shyam Pandey wrote:
> Reset DMA channel after stop to ensure that pending transfers and FIFOs
> in the datapath are flushed or completed. It fixes intermittent data
> verification failure reported by xilinx dma test client.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
> ---
> drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index a9c5d5c..6f1539c 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan)
> u32 reg;
> int err;
>
> - if (chan->cyclic)
> - xilinx_dma_chan_reset(chan);
So reset is required for non cyclic cases as well now?
> -
> - err = chan->stop_transfer(chan);
> - if (err) {
> - dev_err(chan->dev, "Cannot stop channel %p: %x\n",
> - chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
> - chan->err = true;
> + if (!chan->cyclic) {
> + err = chan->stop_transfer(chan);
no stop for cyclic now..?
> + if (err) {
> + dev_err(chan->dev, "Cannot stop channel %p: %x\n",
> + chan, dma_ctrl_read(chan,
> + XILINX_DMA_REG_DMASR));
> + chan->err = true;
> + }
> }
>
> + xilinx_dma_chan_reset(chan);
> /* Remove and free all of the descriptors in the lists */
> xilinx_dma_free_descriptors(chan);
> chan->idle = true;
> --
> 2.7.4
--
~Vinod
