On 06-06-19, 09:19, Sameer Pujar wrote: > > you are really going other way around about the whole picture. FWIW that > > is how *other* folks do audio with dmaengine! > I discussed this internally with HW folks and below is the reason why DMA > needs > to know FIFO size. > > - FIFOs reside in peripheral device(ADMAIF), which is the ADMA interface to > the audio sub-system. > - ADMAIF has multiple channels and share FIFO buffer for individual > operations. There is a provision > to allocate specific fifo size for each individual ADMAIF channel from the > shared buffer. > - Tegra Audio DMA(ADMA) architecture is different from the usual DMA > engines, which you described earlier. > - The flow control logic is placed inside ADMA. Slave peripheral > device(ADMAIF) signals ADMA whenever a > read or write happens on the FIFO(per WORD basis). Please note that the > signaling is per channel. There is > no other signaling present from ADMAIF to ADMA. > - ADMA keeps a counter related to above signaling. Whenever a sufficient when is signal triggered? When there is space available or some threshold of space is reached? > space is available, it initiates a transfer. > But the question is, how does it know when to transfer. This is the > reason, why ADMA has to be aware of FIFO > depth of ADMAIF channel. Depending on the counters and FIFO depth, it > knows exactly when a free space is available > in the context of a specific channel. On ADMA, FIFO_SIZE is just a value > which should match to actual FIFO_DEPTH/SIZE > of ADMAIF channel. That doesn't sound too different from typical dmaengine. To give an example of a platform (and general DMAengine principles as well) I worked on the FIFO was 16 word deep. DMA didn't knew! Peripheral driver would signal to DMA when a threshold is reached and DMA would send a burst controlled by src/dst_burst_size. For example if you have a FIFO with 16 words depth, typical burst_size would be 8 words and peripheral will configure signalling for FIFO having 8 words, so signal from peripheral will make dma transfer 8 words. Here the peripheral driver FIFO is important, but the driver configures it and sets burst_size accordingly. So can you explain me what is the difference here that the peripheral cannot configure and use burst size with passing fifo depth? > - Now consider two cases based on above logic, > * Case 1: when DMA_FIFO_SIZE > SLAVE_FIFO_SIZE > In this case, ADMA thinks that there is enough space available for > transfer, when actually the FIFO data > on slave is not consumed yet. It would result in OVERRUN. > * Case 2: when DMA_FIFO_SIZE < SLAVE_FIFO_SIZE > This is case where ADMA won’t transfer, even though sufficient space is > available, resulting in UNDERRUN. > - The guideline is to program, DMA_FIFO_SIZE(on ADMA side) = > SLAVE_FIFO_SIZE(on ADMAIF side) and hence we need a > way to communicate fifo size info to ADMA. -- ~Vinod
