> -----Original Message----- > From: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Sent: 2019年5月22日 18:10 > Hi Robin, > > Am Mittwoch, den 22.05.2019, 09:59 +0000 schrieb Robin Gong: > > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO > > transfer to be send twice in DMA mode. Please get more information from: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww. > > I haven't tested this so asking the obvious question: what happens when this > series is applied without the RAM script being present on the system? Will it > render SPI unusable? I guess so since it changes the flow between the SPI core > and DMA controller. Can we somehow detect that SDMA isn't using the correct > RAM script and fall back to PIO mode in the SPI driver in that case? > > Currently using the RAM script is not an option in a lot of use-cases, as it still > breaks serial DMA support. The fix for the serial issue really needs to be > remove the broken serial script from the RAM firmware, not change the serial > driver to deal with the broken behavior introduced by the RAM script. Okay, I'll try to merge another patch which fix UART driver function broken issue with ram script so that no any broken for this patch set. > > Regards, > Lucas
