On 04-05-19, 23:37, Paul Cercueil wrote: > When a multi-descriptor DMA transfer is in progress, the "IRQ pending" > flag will apparently be set for that channel as soon as the last > descriptor loads, way before the IRQ actually happens. This behaviour > has been observed on the JZ4725B, but maybe other SoCs are affected. > > In the case where another DMA transfer is running into completion on a > separate channel, the IRQ handler would then run the completion handler > for our previous channel even if the transfer didn't actually finish. > > Fix this by checking in the completion handler that we're indeed done; > if not the interrupted DMA transfer will simply be resumed. Applied, thanks -- ~Vinod
