On 10-10-18, 09:02, Pierre Yves MORDRET wrote: > > > On 10/10/2018 06:03 AM, Vinod wrote: > > On 09-10-18, 10:40, Pierre Yves MORDRET wrote: > >> > >> > >> On 10/07/2018 06:00 PM, Vinod wrote: > >>> On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > >>>> This patch adds support of DMA/MDMA chaining support. > >>>> It introduces an intermediate transfer between peripherals and STM32 DMA. > >>>> This intermediate transfer is triggered by SW for single M2D transfer and > >>>> by STM32 DMA IP for all other modes (sg, cyclic) and direction (D2M). > >>>> > >>>> A generic SRAM allocator is used for this intermediate buffer > >>>> Each DMA channel will be able to define its SRAM needs to achieve chaining > >>>> feature : (2 ^ order) * PAGE_SIZE. > >>>> For cyclic, SRAM buffer is derived from period length (rounded on > >>>> PAGE_SIZE). > >>> > >>> So IIUC, you chain two dma txns together and transfer data via an SRAM? > >> > >> Correct. one DMA is DMAv2 (stm32-dma) and the other is MDMA(stm32-mdma). > >> Intermediate transfer is between device and memory. > >> This intermediate transfer is using SDRAM. > > > > Ah so you use dma calls to setup mdma xtfers? I dont think that is a > > good idea. How do you know you should use mdma for subsequent transfer? > > > > When user bindings told to setup chaining intermediate MDMA transfers are always > triggers. > For instance if a user requests a Dev2Mem transfer with chaining. From client > pov this is still a prep_slave_sg. Internally DMAv2 is setup in cyclic mode (in > double buffer mode indeed => 2 buffer of PAGE_SIZE/2) and destination is SDRAM. > DMAv2 will flip/flop on those 2 buffers. > At the same time DMAv2 driver prepares a MDMA SG that will fetch data from those > 2 buffers in SDRAM and fills final destination memory. I am not able to follow is why does it need to be internal, why should the client not set the two transfers and trigger them? -- ~Vinod
