On Wed, Oct 04, 2017 at 01:38:38AM +0300, Dmitry Osipenko wrote:
> This allows DMA client to issue a non-flow controlled TX. In particular
> it is needed for the fuse driver that reads fuse registers using APBDMA
> to workaround a HW bug that results in hang when CPU and DMA perform
> simultaneous access to fuse peripheral.
>
> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> ---
> drivers/dma/tegra20-apb-dma.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index b9d75a54c896..a177039713a7 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -353,7 +353,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
> }
>
> memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
> - if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {
> + if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
> + sconfig->device_fc) {
> if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
> return -EINVAL;
> tdc->slave_id = sconfig->slave_id;
> @@ -970,8 +971,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
> TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
> ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
>
> - csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
> - csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
> + csr |= TEGRA_APBDMA_CSR_ONCE ;
^^^
Checkpatch should have complained here, no space before ; please
> +
> + if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
> + csr |= TEGRA_APBDMA_CSR_FLOW;
> + csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
> + }
> +
> if (flags & DMA_PREP_INTERRUPT)
> csr |= TEGRA_APBDMA_CSR_IE_EOC;
>
> @@ -1110,10 +1116,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
> TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
> ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
>
> - csr |= TEGRA_APBDMA_CSR_FLOW;
> + if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
> + csr |= TEGRA_APBDMA_CSR_FLOW;
> + csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
> + }
> +
> if (flags & DMA_PREP_INTERRUPT)
> csr |= TEGRA_APBDMA_CSR_IE_EOC;
> - csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
>
> apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
>
> --
> 2.14.1
>
> --
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--
~Vinod
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