NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, supports AHB <-> Memory and Memory <-> Memory transfers, slave / master modes. This driver is primarily supposed to be used by gpu/host1x in a master mode, performing 3D HW context stores. Change log: v2: - Addressed v1 review comments - Added DT header that defines REQ_SEL / TRIG_SEL values Dmitry Osipenko (3): dt-bindings: Add DT binding for NVIDIA Tegra AHB DMA controller dmaengine: Add driver for NVIDIA Tegra AHB DMA controller ARM: dts: tegra: Add AHB DMA controller nodes .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 + arch/arm/boot/dts/tegra20.dtsi | 9 + arch/arm/boot/dts/tegra30.dtsi | 9 + drivers/dma/Kconfig | 10 + drivers/dma/Makefile | 1 + drivers/dma/tegra20-ahb-dma.c | 630 +++++++++++++++++++++ include/dt-bindings/dma/tegra-ahb-dma.h | 56 ++ 7 files changed, 738 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt create mode 100644 drivers/dma/tegra20-ahb-dma.c create mode 100644 include/dt-bindings/dma/tegra-ahb-dma.h -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
