On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote: > NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, > supports AHB <-> Memory and Memory <-> Memory transfers, slave / master > modes. This driver is primarily supposed to be used by gpu/host1x in a > master mode, performing 3D HW context stores. > > Dmitry Osipenko (5): > clk: tegra: Add AHB DMA clock entry > clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20 > dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller > dmaengine: Add driver for NVIDIA Tegra AHB DMA controller > ARM: dts: tegra: Add AHB DMA controller nodes I don't think they are dependent, so consider sending them separately -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
