On Mon, Aug 21, 2017 at 09:35:47AM -0700, Dave Jiang wrote: > On 07/20/2017 11:34 PM, Vinod Koul wrote: > > On Wed, Jul 19, 2017 at 07:25:41PM -0400, Ujjal Singh wrote: > >> We observed performance increase with DMA copy from memory > >> to MMIO by changing the interrupt coalescing value to 0. > >> The previous set value was projected on the C5xxx Xeon > >> platform and no longer holds true. Removing hard coded > >> value and providing a tune-able in sysfs in order to allow > >> user to tune this on a per channel basis. By default this > >> value will be set to 0. > >> Example of sysfs variable importing for interrupt coalescing > >> value from command line: > >> echo 5> /sys/devices/pci0000:00/0000:00:04.0/dma/dma0chan0/ > >> quickdata/intr_coalesce > >> > >> Reported-by: Nithin Sujir <nsujir@xxxxxxxxxx> > >> Signed-off-by: Ujjal Singh <ujjal.singh@xxxxxxxxx> > >> --- > >> V2: Addressed Dave's comments: > >>> Removed definition INTR_DELAY_REG_LIMIT in hw.h and used > >>> existing definition IOAT_INTRDELAY_MASK instead to check > >>> interrupt delay limit in sysfs.c > >> > >> Vinod's comment about ABI doc will come in a different patch > >> to add ABI doc for ioatdma. > > > > Sure, but we should send that first and add ABI documentation for this new > > file in current patch or part of this series > > This one can go in now right? Yes but please rebase and resend -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
