Re: [PATCH 4/5] dmaengine: xilinx_dma: fix hardcoded maximum transfer length may be wrong

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On Fri, Jan 20, 2017 at 04:32:48PM +0100, Andrea Merello wrote:
> The maximumum trasfer length is currently hardcoded in the driver, but
> it depends by how the soft-IP is actually configuried.

/s/configuried/configured

> This seems to affect also max possible length for SG transfers.
> 
> This patch introduce a new DT property in order to operate with proper
> maximum trasfer length.
> 
> Signed-off-by: Andrea Merello <andrea.merello@xxxxxxxxx>
> ---
>  drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 33c0949..cbd8d8c 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -409,6 +409,7 @@ struct xilinx_dma_device {
>  	struct clk *rxs_clk;
>  	u32 nr_channels;
>  	u32 chan_id;
> +	int max_transfer;
>  };
>  
>  /* Macros */
> @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
>  			 * the next chuck start address is aligned
>  			 */
>  			copy = sg_dma_len(sg) - sg_used;
> -			if (copy > XILINX_DMA_MAX_TRANS_LEN)
> -				copy = XILINX_DMA_MAX_TRANS_LEN &
> +			if (copy > chan->xdev->max_transfer)
> +				copy = chan->xdev->max_transfer &
>  					chan->copy_mask;
>  
>  			hw = &segment->hw;
> @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
>  			 * the next chuck start address is aligned
>  			 */
>  			copy = period_len - sg_used;
> -			if (copy > XILINX_DMA_MAX_TRANS_LEN)
> -				copy = XILINX_DMA_MAX_TRANS_LEN &
> +			if (copy > chan->xdev->max_transfer)
> +				copy = chan->xdev->max_transfer &
>  					chan->copy_mask;
>  
>  			hw = &segment->hw;
> @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
>  	struct xilinx_dma_device *xdev;
>  	struct device_node *child, *np = pdev->dev.of_node;
>  	struct resource *io;
> -	u32 num_frames, addr_width;
> +	u32 num_frames, addr_width, lenreg_width;
>  	int i, err;
>  
>  	/* Allocate and initialize the DMA engine structure */
> @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device *pdev)
>  		return PTR_ERR(xdev->regs);
>  
>  	/* Retrieve the DMA engine properties from the device tree */
> -	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
> +	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
>  		xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
> +		err = of_property_read_u32(node, "xlnx,lengthregwidth",
> +					   &lenreg_width);

ah you are using a property for this, where is this added??

> +		if (err < 0) {
> +			dev_err(xdev->dev,
> +				"missing xlnx,lengthregwidth property\n");
> +			return err;
> +		}
> +		xdev->max_transfer = GENMASK(lenreg_width, 0);
> +	}
>  
>  	if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
>  		err = of_property_read_u32(node, "xlnx,num-fstores",
> -- 
> 2.7.4
> 

-- 
~Vinod
--
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