Mason <slash.tmp@xxxxxxx> writes: > On 25/11/2016 16:12, Måns Rullgård wrote: > >> Mason writes: >> >>> I've had several talks with the HW dev, and I don't think they >>> anticipated the need to mux the 3 channels. In their minds, >>> customers would choose at most 3 devices to support, and >>> assign one channel to each device statically. >>> >>> In fact, in tango4, supported devices are: >>> A) NAND Flash controllers 0 and 1 >>> NB: the upstream driver only uses controller 0 >>> B) IDE or SATA controllers 0 and 1 >>> C) a few crypto HW blocks which do not work as expected (unused) >>> >>> Customers typically use 1 channel for NAND, maybe 1 for SATA, >>> and 1 channel remains unused. >> >> The hardware has two sata controllers, and I have a board that uses both. > > I don't have the tango3 client devices in mind, but > 1 NAND + 2 SATA works out alright for 3 channels, right? There are only two usable channels. Besides, your 3.4 kernel allocates the channels dynamically, sort of, but since it has a completely custom api, this particular timing issue doesn't arise there. -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
