On 06/21/2016 01:07 PM, Andy Shevchenko wrote:
Fix this by calculating and setting the destination memory width after
splitting by using the split block aligment and length.
I think the problem is deeper than that.
The caller in the best case can provide already split buffer based on
max_segment_size parameter from struct dma_parms. We have to fill it in
the DMA controller driver, i.e. dw_dmac, properly.
Problem with max_segment_size that it is static but here optimal buffer
split depends on runtime parameter - for instance register width in
device to memory transfers. Which may not be known when
dma_get_max_seg_size() is called.
The problem here that all infrastructure around it relies on the
parameters of DMA device as a whole, when we should rely on parameters
of _individual channel_.
Fortunately dw_dmac internal buffer splitting uses per channel block
size at least on HW that has this autocfg bit. But I agree
dma_get_max_seg_size(dev) appears to be limited for DMA engine users if
channels have different parameters or is dependent on other runtime
parameters.
--
Jarkko
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