On 2016-06-18 22:02, Wolfram Sang wrote:
We run the command i2cdetect for address 0x3 to 0x77. The QUP
generates
write error for address 0x3 to 0x7 apart from other bus errors since
these are reserved addresses. I was getting the crash in non DMA mode
and BAM hang in DMA mode before putting the fix.
Also we have connected the I2C TPM and run the following script
overnight for both DMA and Non DMA mode. The script checks for
all transfer length and we are generating multiple NACK and
Non NACK error before each valid transfer.
a=1
while [ $a -lt 4096 ]
do
echo $a
i2cdetect -y -a -r 0 0x03 0x77
tpm-manager get_random $a
i2cdetect -y -a -r 1 0x03 0x77
a=`expr $a + 1`
done
So, what is the outcome of this discussion?
Discussion was regarding resetting the QUP state in ISR and it is the
part of
existing code itself. The current patch only added the error checking
for bus
errors so we can go ahead with this patch. I have shared the script
which we
are using for testing error path.
--
To unsubscribe from this list: send the line "unsubscribe dmaengine" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
