On Wed, Dec 02, 2015 at 04:47:43PM -0600, Han Xu wrote: > By default NAND driver will choose the highest ecc strength that oob > could contain, in this case, for some 8K+744 NAND flash, the ecc > strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability > (40bit). > > This patch allows the NAND driver try to use minimum required ecc > strength if it failed to use the highest ecc, even without explicitly > claiming "fsl,use-minimum-ecc" in dts. > > Signed-off-by: Han Xu <b45815@xxxxxxxxxxxxx> Pushed this one to l2-mtd.git/next too. Would it help to implement support for the "nand-ecc-step-size" and "nand-ecc-strength" properties sometime? That would be more maintainable, as it's more specific. What if you need a little stronger than the minimum ECC? You also are relying on not changing the default behavior of the driver, for the "legacy" ECC calculation still. That ties your hands a bit. Brian -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
