Hi Mark, > +5. A 32bit mask specifying the DMA FIFO configuration > + -bit 0-1: Fifo threshold > + 0x0: 1/4 full FIFO > + 0x1: 1/2 full FIFO > + 0x2: 3/4 full FIFO > + 0x3:full FIFO > + -bit 2: Direct mode > + 0x0: enabled > + 0x1: disabled > + Finally, I find a way to handle the above inputs outside DT. So, I will remove it from DT in the next version. Thanks. To sum-up, the remaining information that the client will have to specify from DT are describing below. Is it ok ? > + -bit 9: Peripheral Increment Address > + 0x0: no address increment between transfers > + 0x1: increment address between transfers > + -bit 10: Memory Increment Address > + 0x0: no address increment between transfers > + 0x1: increment address between transfers > + -bit 15: Peripheral Increment Offset Size > + 0x0: offset size is linked to the peripheral bus width > + 0x1: offset size is fixed to 4 (32-bit alignment) > + -bit 16-17: Priority level > + 0x0: low > + 0x1: medium > + 0x2: high > + 0x3: very high BR, Cedric -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
