HI, On Sun, Jun 28, 2015 at 5:45 PM, Vinod Koul <vinod.koul@xxxxxxxxx> wrote: [...] >> > I asked how the device address in configured. For both MM2S S2MM you are >> > using sg for memory address, where are you getting device adress, are you >> > assuming/hardcoding or getting somehow, if so how? >> As the name says, one end is memory (MM) and the other end is an AXI4 >> Stream Bus (S) which has no concept of memory address. >> So yes, it is hardcoded at design time. > So where does the data go at the end of stream bus, who configures that? > Shouldnt all this be at least documented... You make the connection at design time. In Zynq7000 case, there's a dual core Cortex A9 coupled with an FPGA. While designing the FPGA part, you instantiate an Xilinx AXI DMA, on one side you connect it to an AXI4 Lite bus (which is memory mapped) and on the other side you connect your custom peripheral using an AXI4 Stream bus which has no concept of addresses. Here's a picture which depicts all of this [0]. Does this clear things up? [0] http://www.fpgadeveloper.com/wp-content/uploads/2014/08/fpga_developer_20140806_130447.png -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
