On Tue, Apr 28, 2015 at 11:03:20AM +0200, Maxime Ripard wrote:
> The XDMAC DMA controller uses a concept of views to be able to handle
> descriptors of different sizes.
>
> So far, only the views 1 and 2 were handled by the driver. Unfortunately, we
> need some of the configuration fields found in the view 3 in order to support
> memset and interleaved transfers.
>
> Add the definition for the view 3 registers, and the needed code to handle view
> 3 descriptors.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx>
Acked-by: Ludovic Desroches <ludovic.desroches@xxxxxxxxx>
> ---
> drivers/dma/at_xdmac.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
> index 933e4b338459..2d039512ecb3 100644
> --- a/drivers/dma/at_xdmac.c
> +++ b/drivers/dma/at_xdmac.c
> @@ -236,6 +236,10 @@ struct at_xdmac_lld {
> dma_addr_t mbr_sa; /* Source Address Member */
> dma_addr_t mbr_da; /* Destination Address Member */
> u32 mbr_cfg; /* Configuration Register */
> + u32 mbr_bc; /* Block Control Register */
> + u32 mbr_ds; /* Data Stride Register */
> + u32 mbr_sus; /* Source Microblock Stride Register */
> + u32 mbr_dus; /* Destination Microblock Stride Register */
> };
>
>
> @@ -359,6 +363,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
> if (at_xdmac_chan_is_cyclic(atchan)) {
> reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
> at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
> + } else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) {
> + reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
> } else {
> /*
> * No need to write AT_XDMAC_CC reg, it will be done when the
> --
> 2.3.6
>
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