> On 15.04.2015, at 11:56, Noralf Trønnes <noralf@xxxxxxxxxxx> wrote: > +#define MAX_LITE_TRANSFER (SZ_64K - 1) > +#define MAX_NORMAL_TRANSFER SZ_1G ... > + if (c->ch >= 8) /* LITE channel */ > + max_size = MAX_LITE_TRANSFER; > + else > + max_size = MAX_NORMAL_TRANSFER; > + period_len = min(period_len, max_size); > + d->frames = (buf_len - 1) / (period_len + 1); I wonder if it is wise to split the transfers on 65535 bytes for the Lite DMA-channels - especially if you are transferring to word size registers (like SPI_FIFO), you still push 16384 words into the register and the last word of this transfer (word 16384) still is assumed 4 valid bytes by the device and thus gets operated upon - even if the last byte contains garbage from the DMA-transfer point of view. So maybe it is better to separate on SZ_64K-4 or better still SZ_32K to be on a power of 2 address boundary.-- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
