On Tue, Jan 13, 2015 at 11:28 PM, Vinod Koul <vinod.koul@xxxxxxxxx> wrote: > On Fri, Jan 02, 2015 at 05:01:42PM +0530, Mayuresh Chitale wrote: > > 1st things stop TOP posting, this is not good email etiquette... > >> The DMA engine is actually a part of a PCI root complex and uses >> memory mapped FIFOs for both sides i.e AXI and PCI and we need to >> program memory mapped queues for both AXI side and PCI side. Its >> possible that there could be multiple elements from AXI side that need >> to be transferred to multiple elements to PCI side or vice-versa >> provided that the total length on both sides is equal. I see there is >> the device_prep_dma_sg api but it appears to me that is only intended >> to be used for async operations. Is that correct? > the FIFO will have constant address or will it increment/decrement? Actually the queues are descriptor queues only. We have to provide to hardware information about source, destination and status queues which are initialized during probe. Each element of source/destination queue contains information about the actual address and some other attributes. The source/destination address can be in either PCI or AXI address. In this case dmaengine APIs are expected to program elements with proper address etc. I would describe it as a special case of mem2mem transfer between Host DDR and PCI address space. Is it ok in this case to support memcpy and sg apis? However this device cannot be used for these operations between two memory locations on the same host. Besides I would also need to know direction to determine whether source/destination address points to PCI or AXI location. In normal mem2mem transfers there is no use for direction. > > -- > ~Vinod > >> >> On Fri, Jan 2, 2015 at 4:51 PM, Lars-Peter Clausen <lars@xxxxxxxxxx> wrote: >> > On 01/02/2015 12:09 PM, Mayuresh Chitale wrote: >> >> >> >> Yes. That is correct. >> > >> > >> > Ok, but please explain in detail what exactly your use case is for this for >> > slave-device DMA. For a device you usually have either a dedicated DMA port >> > to which the DMA controller is directly connected or a memory mapped FIFO. >> > So there really is only one source or destination when reading from a device >> > or writing to a device. >> > >> > >> >> >> >> Thanks, >> >> Mayuresh. >> >> >> >> On Fri, Jan 2, 2015 at 4:39 PM, Lars-Peter Clausen <lars@xxxxxxxxxx> >> >> wrote: >> >>> >> >>> On 01/02/2015 12:03 PM, Mayuresh Chitale wrote: >> >>>> >> >>>> >> >>>> Hi, >> >>>> >> >>>> I am working on a slave dma driver that supports scatter-gather >> >>>> operation. However looking at APIs in dmaengine.h I see that the >> >>>> device_prep_slave_sg supports only many to one transfer. Is there any >> >>>> API that can be used to support many to many transfers for slave dma? >> >>> >> >>> >> >>> >> >>> What do you mean by many to many? Many sources to many destinations? >> >>> >> >>> - Lars >> >>> >> > >> -- >> To unsubscribe from this list: send the line "unsubscribe dmaengine" in >> the body of a message to majordomo@xxxxxxxxxxxxxxx >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > -- -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
