Hi Vinod
Thank you for youre review
Basically, this DMAC is very simple device,
it needs very few settings only.
> > From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
> > +static struct dma_async_tx_descriptor *
> > +audmapp_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
> > + size_t buf_len, size_t period_len,
> > + enum dma_transfer_direction dir, unsigned long flags)
> > +{
> > + struct audmapp_chan *achan = chan_to_achan(chan);
> > +
> > + return &achan->async_tx;
> > +}
> I had commented last time as well. This doesnt look right. You are ignoring
> all input parameters, so how does it work at all?
When we set simple settings to DMAC, then, it works automatically as cyclic transfer.
The usage of this DMA is very limited, so it is super simple.
In addition, this is 2nd DMA which is needed on sound.
1st DMA is controled by rcar-dmac.c
2nd DMA is this
almost all settings are set by 1st DMA, 2nd DMA is just relay.
The necessary settings of this DMAC is only "ID" and "in/out address".
We can get address from DMA_SLAVE_CONFIG,
and, ID from DT settings.
Thus, this dma_cyclic is nothing to do.
I will add this comment on v3, is that OK ?
> > +static int audmapp_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> > + unsigned long arg)
> > +{
> > + struct audmapp_chan *achan = chan_to_achan(chan);
> > +
> > + switch (cmd) {
> > + case DMA_TERMINATE_ALL:
> > + audmapp_halt(achan);
> > + break;
> > + case DMA_SLAVE_CONFIG:
> > + audmapp_slave_config(achan, (struct dma_slave_config *)arg);
> > + break;
> This needs to be updated to new APIs i have merged at
> topic/slave_caps_device_control_fix
I see. will fix
> I don't see any interrupt code, does that get done by some other lib code?
> something seems missing here
This DMAC doesn't have interrupt.
Best regards
---
Kuninori Morimoto
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