Re: [PATCH] dma: dma40: add signal documentation to the device tree bindings

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Wed, Jun 11, 2014 at 10:49:55AM +0200, Linus Walleij wrote:
> The DMA40 device tree documentation was vague on the second cell passed
> in the configuration node for consumers, and did not specify what the
> available signals were connected to. Extend the documentation with this
> information for the DB8500 ASIC.

Applied, thanks


>  1 file changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> index 1f5729f10621..95800ab37bb0 100644
> --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -35,9 +35,11 @@ Required properties:
>  
>  Each dmas request consists of 4 cells:
>    1. A phandle pointing to the DMA controller
> -  2. Device Type
> +  2. Device signal number, the signal line for single and burst requests
> +     connected from the device to the DMA40 engine
>    3. The DMA request line number (only when 'use fixed channel' is set)
> -  4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow]
> +  4. A 32bit mask specifying; mode, direction and endianness
> +     [NB: This list will grow]
>          0x00000001: Mode:
>                  Logical channel when unset
>                  Physical channel when set
> @@ -54,6 +56,74 @@ Each dmas request consists of 4 cells:
>                  Normal priority when unset
>                  High priority when set
>  
> +Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
> +bidirectional, i.e. the same for RX and TX operations:
> +
> +0:  SPI controller 0
> +1:  SD/MMC controller 0 (unused)
> +2:  SD/MMC controller 1 (unused)
> +3:  SD/MMC controller 2 (unused)
> +4:  I2C port 1
> +5:  I2C port 3
> +6:  I2C port 2
> +7:  I2C port 4
> +8:  Synchronous Serial Port SSP0
> +9:  Synchronous Serial Port SSP1
> +10: Multi-Channel Display Engine MCDE RX
> +11: UART port 2
> +12: UART port 1
> +13: UART port 0
> +14: Multirate Serial Port MSP2
> +15: I2C port 0
> +16: USB OTG in/out endpoints 7 & 15
> +17: USB OTG in/out endpoints 6 & 14
> +18: USB OTG in/out endpoints 5 & 13
> +19: USB OTG in/out endpoints 4 & 12
> +20: SLIMbus or HSI channel 0
> +21: SLIMbus or HSI channel 1
> +22: SLIMbus or HSI channel 2
> +23: SLIMbus or HSI channel 3
> +24: Multimedia DSP SXA0
> +25: Multimedia DSP SXA1
> +26: Multimedia DSP SXA2
> +27: Multimedia DSP SXA3
Interesting, So you have a DSP and Slimbus??

-- 
~Vinod
--
To unsubscribe from this list: send the line "unsubscribe dmaengine" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html




[Index of Archives]     [Linux Kernel]     [Linux ARM (vger)]     [Linux ARM MSM]     [Linux Omap]     [Linux Arm]     [Linux Tegra]     [Fedora ARM]     [Linux for Samsung SOC]     [eCos]     [Linux PCI]     [Linux Fastboot]     [Gcc Help]     [Git]     [DCCP]     [IETF Announce]     [Security]     [Linux MIPS]     [Yosemite Campsites]

  Powered by Linux