On Mon, 2014-04-07 at 21:07 +0100, Ben Dooks wrote: > Add support for building shdma internal data from the device tree to allow > converting the driver to be device tree enabled. > > It includes a helper for the of case to build the internal data used to > select and filter out the DMA channels from the ID information in the > device tree. Also updates the documentation for the DT case. Few minor comments below. > --- a/drivers/dma/sh/shdma-of.c > +++ b/drivers/dma/sh/shdma-of.c > @@ -40,6 +71,109 @@ static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec, > return chan; > } > > +const struct sh_dmae_pdata * > +sh_dma_probe_of(struct platform_device *pdev, const struct of_device_id *ofmatch) > +{ > + const struct device_node *np = pdev->dev.of_node; > + const struct sh_dmae_of_info *ofinf; > + struct device *dev = &pdev->dev; > + struct sh_dmae_pdata *pdata; > + struct sh_dmae_channel *chan; > + struct property *prop; > + u32 nr_chan; > + unsigned ch; > + int ret; > + int len; > + > + if (!ofmatch) > + return NULL; > + > + ofinf = ofmatch->data; > + > + pdata = devm_kzalloc(dev, sizeof(struct sh_dmae_pdata), GFP_KERNEL); sizeof(*pdata) ? > + if (!pdata) { > + dev_err(dev, "failed to make platform data\n"); > + return NULL; > + } > + > + *pdata = *ofinf->pdata_template; /* copy in template first */ > + > + ret = of_property_read_u32(np, "dma-channels", &nr_chan); > + if (ret < 0) { > + dev_err(dev, "failed to get number of channels\n"); > + return NULL; > + } > + > + chan = devm_kzalloc(dev, nr_chan * sizeof(struct sh_dmae_channel), > + GFP_KERNEL); devm_kcalloc() > + if (!chan) { > + dev_err(dev, "cannot allocate %d channels\n", nr_chan); > + return NULL; > + } > + > + pdata->channel = chan; > + pdata->channel_num = nr_chan; > + > + dev_dbg(dev, "%d dma channels allocated\n", nr_chan); > + > + for (ch = 0; ch < nr_chan; ch++) { > + struct sh_dmae_channel *cp = chan + ch; > + u32 base = ofinf->channel_offset + ofinf->channel_stride * ch; > + > + cp->offset = base + ofinf->offset; > + cp->dmars = base + ofinf->dmars; > + cp->chclr_bit = ch; > + cp->chclr_offset = ofinf->chclr_offset; > + > + dev_dbg(dev, "ch %d: off %08x, dmars %08x, bit %d, off %d\n", > + ch, cp->offset, cp->dmars, > + cp->chclr_bit, cp->chclr_offset); > + } > + > + /* look in current, or parent node for the slave mappings */ > + prop = of_find_property(np, "renesas,slaves", &len); > + if (!prop) > + prop = of_find_property(np->parent, "renesas,slaves", &len); > + > + if (prop) { > + struct sh_dmae_slave_config *slaves; > + int nr_slaves = len / (sizeof(u32) * 3); > + const __be32 *of_ptr; > + u32 of_idx; > + > + slaves = devm_kzalloc(dev, sizeof(*slaves) * nr_slaves, > + GFP_KERNEL); devm_kcalloc() > + if (!slaves) { > + dev_err(dev, "cannot allocate %d slaves\n", nr_slaves); > + return NULL; > + } > + > + pdata->slave = slaves; > + pdata->slave_num = nr_slaves; > + of_idx = 0; > + of_ptr = NULL; > + > + dev_dbg(dev, "building %d slaves\n", nr_slaves); > + > + for (; nr_slaves > 0; nr_slaves--, slaves++) { > + of_ptr= of_prop_next_u32(prop, of_ptr, &of_idx); > + slaves->mid_rid = be32_to_cpu(*of_ptr); > + slaves->slave_id = slaves->mid_rid; > + > + of_ptr= of_prop_next_u32(prop, of_ptr, &of_idx); > + slaves->chcr = be32_to_cpu(*of_ptr); > + > + dev_dbg(dev, "slave: id %02x, chcr %08x, addr %08x\n", > + slaves->mid_rid, slaves->chcr, slaves->addr); > + } > + } else { > + dev_warn(dev, "did not find any slave information\n"); > + } > + > + pdev->dev.platform_data = pdata; > + return pdata; > +}; -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxx> Intel Finland Oy --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. ��.n��������+%������w��{.n��������)�)��jg��������ݢj����G�������j:+v���w�m������w�������h�����٥