On Thu, Oct 15, 2015 at 11:51 AM, Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx> wrote: > On Thu, Oct 15, 2015 at 10:25:43AM -0400, WingMan Kwok wrote: >> On TI's Keystone platforms, several peripherals such as the >> gbe ethernet switch, 10gbe ethether switch and PCIe controller >> require the use of a SerDes for converting SoC parallel data into >> serialized data that can be output over a high-speed electrical >> interface, and also converting high-speed serial input data >> into parallel data that can be processed by the SoC. The >> SerDeses used by those peripherals, though they may be different, >> are largely similar in functionality and setup. > > Given that serdes is not specific to TI, should this be specific to > TI, or should there be an effort to come up with something which > everyone who has serdes links can make use of? > > Serdes comes in multiple different forms: PCIe, 1G SGMII ethernet, > 1000base-X ethernet, 10g ethernet, SATA... I'd hate to see a > plethora of SoC specific stuff for this. The licensed IP I've seen doesn't provide a standard register interface, but just signals to the IP block. Same with PLL IP. So we'll probably get to see vendors continue to differentiate on PHY register design. :) Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
