On Tue, Oct 13, 2015 at 05:37:56PM +0800, Chaotian Jing wrote:
> Add 400Mhz clock source for HS400 mode
>
> Signed-off-by: Chaotian Jing <chaotian.jing@xxxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> index a1adfa4..745bee2 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
> @@ -17,6 +17,11 @@ Required properties:
> - vmmc-supply: power to the Core
> - vqmmc-supply: power to the IO
>
> +Optional properties:
> +- clocks: 400mhz clock source for HS400
> +- clock-names: "400mhz"
Is that really what the input line is called?
> +- hs400-ds-delay: HS400 DS delay setting
What is the format of this? Where can I derive the correct value?
Mark.
> +
> Examples:
> mmc0: mmc@11230000 {
> compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
> @@ -24,9 +29,12 @@ mmc0: mmc@11230000 {
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
> vmmc-supply = <&mt6397_vemc_3v3_reg>;
> vqmmc-supply = <&mt6397_vio18_reg>;
> - clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
> - clock-names = "source", "hclk";
> + clocks = <&pericfg CLK_PERI_MSDC30_0>,
> + <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
> + <&topckgen CLK_TOP_MSDCPLL_D2> ;
> + clock-names = "source", "hclk", "400mhz";
> pinctrl-names = "default", "state_uhs";
> pinctrl-0 = <&mmc0_pins_default>;
> pinctrl-1 = <&mmc0_pins_uhs>;
> + hs400-ds-delay = <0x14015>;
> };
> --
> 1.8.1.1.dirty
>
>
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