On Thu, Oct 08, 2015 at 05:43:11PM +0800, Ley Foon Tan wrote:
> +static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 value)
> +{
> + struct altera_pcie *pcie = bus->sysdata;
> + u32 data32;
> + u32 shift = 8 * (where & 3);
> + int ret;
> +
> + if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + /* write partial */
> + if (size != sizeof(u32)) {
> + ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
> + where & ~DWORD_MASK, &data32);
> + if (ret)
> + return ret;
> + }
> +
> + switch (size) {
> + case 1:
> + data32 = (data32 & ~(0xff << shift)) |
> + ((value & 0xff) << shift);
> + break;
> + case 2:
> + data32 = (data32 & ~(0xffff << shift)) |
> + ((value & 0xffff) << shift);
> + break;
> + default:
> + data32 = value;
Can you generate proper 1, 2 and 4 byte configuration accesses? That
is much preferred over the above read-modify-write, as there are
registers in PCI and PCIe that are read/write-1-to-clear. The above
has the effect of inadvertently clearing those RW1C bits.
--
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
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