From: Martin Sperl <kernel@xxxxxxxxxxxxxxxx>
The bcm2835 SOC has an auxiliary uart that is compatible to ns16550.
the only difference is that it has an internal clock divider of 8
instead of 16.
The net result is that the baud-rate is twice the baud-rate requested.
This patch allows to configure an alternate clock-divider in the
device-tree, which then scales the clock coming from the clock
framework to get scaled by 16/divider.
Signed-off-by: Martin Sperl <kernel@xxxxxxxxxxxxxxxx>
---
drivers/tty/serial/of_serial.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index afae58a..2fcbfee 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -65,6 +65,7 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
struct resource resource;
struct device_node *np = ofdev->dev.of_node;
u32 clk, spd, prop;
+ u64 clk_scaled;
int ret;
memset(port, 0, sizeof *port);
@@ -84,6 +85,19 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
clk = clk_get_rate(info->clk);
}
+ /* a custom clock divider instead of the default 16
+ * this (as of now) does not change the low level behaviour
+ * but only scales the clock accordingly
+ */
+ if (of_property_read_u32(np, "clock-divider", &spd) == 0) {
+ clk_scaled = (u64) clk * 16;
+ do_div(clk_scaled, spd);
+ dev_info(&ofdev->dev,
+ "scaling clock %uHz to %uHz to allow a clock divider of %u\n",
+ clk, (u32)clk_scaled, spd);
+ clk = (u32) clk_scaled;
+ }
+
/* If current-speed was set, then try not to change it. */
if (of_property_read_u32(np, "current-speed", &spd) == 0)
port->custom_divisor = clk / (16 * spd);
--
1.7.10.4
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