Add fw_cfg DMA interface specfication in the fw_cfg documentation. Signed-off-by: Marc Marí <markmb@xxxxxxxxxx> --- Documentation/devicetree/bindings/arm/fw-cfg.txt | 51 +++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt b/Documentation/devicetree/bindings/arm/fw-cfg.txt index 953fb64..766ddbe 100644 --- a/Documentation/devicetree/bindings/arm/fw-cfg.txt +++ b/Documentation/devicetree/bindings/arm/fw-cfg.txt @@ -45,6 +45,53 @@ blob to be read from the data register has size 4, and it is to be interpreted as a uint32_t value in little endian byte order. The current value (corresponding to the above outer protocol) is zero. +If bit 1 of the feature bitmap is set, the DMA interface is present. This +can be used through the 64-bit wide address register. + +The address register is in big-endian format. The value for the register is 0 +at startup and after an operation. A write to the lower half triggers an +operation. This means, that operations with 32-bit addresses can be triggered +with just one write, whereas operations with 64-bit addresses can be triggered +with one 64-bit write or two 32-bit writes, starting with the higher part. + +In this register, a physical RAM address to a FWCfgDmaAccess structure should +be written. This is the format of the FWCfgDmaAccess structure: + +typedef struct FWCfgDmaAccess { + uint32_t control; + uint32_t length; + uint64_t address; +} FWCfgDmaAccess; + +The fields of the structure are in big endian mode, and the field at the lowest +address is the "control" field. + +The "control" field has the following bits: + - Bit 0: Error + - Bit 1: Read + - Bit 2: Skip + +When an operation is triggered, if the "control" field has bit 1 set, a read +operation will be performed. "length" bytes for the current selector and +offset will be copied into the address specified by the "address" field. + +If the control field has only bit 2 set, a skip operation will be perfomed. +The offset for the current selector will be advanced "length" bytes. + +To check result, read the "control" field: + error bit set -> something went wrong. + all bits cleared -> transfer finished successfully. + otherwise -> transfer still in progress (doesn't happen + today due to implementation not being async, + but may in the future). + +Target address goes up and transfer length goes down as the transfer happens, +so after a successful transfer the length field is zero and the address field +points right after the memory block written. + +If a partial transfer happened before an error occured the address and +length registers indicate how much data has been transfered successfully. + The guest kernel is not expected to use these registers (although it is certainly allowed to); the device tree bindings are documented here because this is where device tree bindings reside in general. @@ -56,6 +103,8 @@ Required properties: - reg: the MMIO region used by the device. * Bytes 0x0 to 0x7 cover the data register. * Bytes 0x8 to 0x9 cover the selector register. + * With DMA interface enabled: Bytes 0xc to 0x13 cover the DMA address + register. * Further registers may be appended to the region in case of future interface revisions / feature bits. @@ -66,7 +115,7 @@ Example: #address-cells = <0x2>; fw-cfg@9020000 { + reg = <0x0 0x9020000 0x0 0x14>; compatible = "qemu,fw-cfg-mmio"; - reg = <0x0 0x9020000 0x0 0xa>; }; }; -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html