On Wed, Aug 19, 2015 at 02:49:26PM +0900, Masahiro Yamada wrote: > This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings > document says that the bits[15:8] of the 3rd cell of the interrupts > property represents PPI interrupt CPU mask. Because the timer > interrupts are wired to all of the 4 cores, bits[15:8] should be set > to 0xf. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> > --- > > Changes in v2: > - Fix git-description Thanks, applied. -Olof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
