On Thursday, August 20, 2015 at 11:18:14 AM, Viet Nga Dao wrote: Hi, [...] > >> That is why we decided to upstream the > >> driver. If the hardware fix, there might not need to have any changes > >> in driver to support or if yes, it will be just minor. > > > > If the hardware can do proper READID opcode, this entire nonsense table > > will go away and a proper integration into the SPI NOR framework will > > take place. > > > > You might consider submitting this driver for staging, but I definitely > > am not a big fan of that. > > You might misunderstand the hardware problem i mention here. This soft > IP controller is able to provide the ID for our Altera EPCS/EPCQ flash > chips, which are non JEDEC chips. As from EPCQ device data sheet > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature > /hb/cfg/cfg_cf52012.pdf), the device ID is 8 bit data. So what exactly is the output of READID instruction followed by 6 Byte read on an EPCQ chip? > The remaining > problem here is that this controller is able to support Micron chips but > it currently has > limitation in providing only 8 bit ID, which is not full JEDEC ID for > Micron chips. OK > Hence, we are asking hardware engineer to find out the > solution so that the driver does not need to do any dirty hacking. And > so, this table should still be here even hardware fix will take place > or not. [...] Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
