On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: > I'm not very helpful here, so hopefully Viet can be of more use: Yup :) > On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > > Also, I cannot find any documentation for this IP block even if I search > > through Quartus/QSys, is there any proper documentation available > > anywhere? > > I never found proper documentation, but I didn't look too hard. I've > mostly been going off of Viet's comments and code. Me neither, and I looked through the altera stuff in fact. I'm trying to learn whether this is just an Soft IP, in which case it certainly can be fixed ; or if there is actually some chip shipping with this crap synthesised into actual silicon. > But FWIW, I did find some relevant info for the peculiar Altera EPCQ > flash here: > > https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ > hb/cfg/cfg_cf52012.pdf Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just have different JEDEC ID and are a bit more expensive. Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
