On 06/10, Daniel Thompson wrote: > The driver supports decoding and statically modelling PLL state (i.e. > we inherit state from bootloader) and provides support for all > peripherals that support simple one-bit gated clocks. The covers all > peripherals whose clocks come from the AHB, APB1 or APB2 buses. > > It has been tested on an STM32F429I-Discovery board. The clock counts > for TIM2, USART1 and SYSTICK are all set correctly and the wall clock > looks OK when checked with a stopwatch. I have also tested a prototype > driver for the RNG hardware. The RNG clock is correctly enabled by the > framework (also did inverse test and proved that by changing DT to > configure the wrong clock bit then we observe the RNG driver to fail). > > Signed-off-by: Daniel Thompson <daniel.thompson@xxxxxxxxxx> > Reviewed-by: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in
