Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> writes:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..12430f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,16 @@
> <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt8173-scpsys";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = <&clk26m>,
> + <&topckgen CLK_TOP_MM_SEL>;
Neither your binding doc (nor the generic one) mentions these clock
properties or what they are used for. They appear to define a clock
that must be enabled in order to for the power domain to be on.
Also the order here seems rather important and probably needs
documenting in the binding (e.g. the clk_id order is hard-coded in the
driver.)
Kevin
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