Describe the L1 instruction and data caches in the CPU nodes:
- The L1 instruction caches for the Cortex-A7 CPU cores are organized
as 16 KiB x 2 ways,
- The L1 data caches for the Cortex-A7 CPU cores are organized as 8
KiB x 4 ways.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
arch/arm/boot/dts/r8a7794.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 0c3ab5febe0a88d8..0ea502a43d553e25 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -28,6 +28,16 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
+
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA7>;
};
cpu1: cpu@1 {
@@ -35,6 +45,16 @@
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
+
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA7>;
};
};
--
1.9.1
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